Switching regulator with automatic multi mode conversion

ABSTRACT

Methods and apparatus are disclosed for efficient switching regulators that adapt automatically to, and operate with, input voltages that are above, below, or equal to the output voltage. The disclosed switching regulators demonstrate advantages of both buck and boost converters at high efficiency.

TECHNICAL FIELD

The embodiments described below relate, in general, to switch mode power supplies and, in particular, to efficient and automatic switching regulators operating from input voltages that are above, below, or equal to the output voltage.

BACKGROUND

Switch mode power supply (SMPS) is popular in powering ASICs, DRAMs, and other electronic devices because of its high efficiency. The selection of the SMPS topology requires consideration of the relationship of the input and output voltages. In some applications, the input voltage may be above, below, or equal to the output voltage.

One example is the portable devices such as digital cameras that use a single-cell Li-lon battery to power a 3.3V rail, where the battery voltage is about 4.2V after charging up and drops to about 2.7V before the camera ceases to function. Appropriate efficiency is also required during the entire range of operation to maximize the battery usage life despite its limited size and weight. Such applications require SMPS's that can operate efficiently and automatically with input voltages that are above, below, or equal to the output voltage.

A buck converter can only be used if an input voltage remains higher than the output voltage. On the other hand, a boost converter may only be used if the input voltage stays less than the output voltage at all times. The well-known buck-boost converter can operate automatically from input voltages above, below, or equal to the output voltage, but cannot maintain a high efficiency over a wide range of input voltages. The buck-boost converter has a reasonable efficiency only when the input voltage is close to the output voltage, but it has much less efficiency than a buck converter when the input voltage is above the output voltage and much less than a boost converter when input voltage is below the output voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of different parts of an automatic multimode converter, in accordance with an embodiment of the invention.

FIG. 2 shows operation waveforms of the automatic multimode converter shown in FIG. 1.

FIG. 3 shows an example of implementation details of the automatic multimode converter shown in FIG. 1.

FIG. 4 shows another example of implementation details of the automatic multimode converter shown in FIG. 1.

DETAILED DESCRIPTION

Various embodiments of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of these embodiments. One skilled in the art will understand, however, that the invention may be practiced without many of these details. Additionally, some well-known structures or functions may not be shown or described in detail, so as to avoid unnecessarily obscuring the relevant description of the various embodiments.

The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific embodiments of the invention. Certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section.

The description of the embodiments of the invention and their applications as set forth herein is illustrative and is not intended to limit the scope of the invention. Variations and modifications of the embodiments are possible and practical alternatives to, or equivalents of the various elements of, the embodiments disclosed herein and are known to those of ordinary skill in the art. Such variations and modifications of the disclosed embodiments may be made without departing from the scope and spirit of the invention.

The following detailed description discloses methods and apparatus for efficient and automatic multimode SMPS's with input voltages that are above, below, or equal to the output voltages. FIG. 1 shows a schematic diagram of different parts of an automatic multimode converter. The power stage shown in FIG. 1A includes four switches that are all actively controlled. S₁ is referred to as the buck switch, and S₃ is referred to as the boost switch. The power stage converts an input voltage to a desired output voltage.

The control circuit shown in FIG. 1B, sends two control signals D₁ and D₂ to switch drivers of S₁ to S₄. When D₁=“H” (High), S₁ is on and S₂ is off; and when D₁=“L” (Low), S₁ is off and S₂ is on. When D₂=“H”, S₃ is on and S₄ is off; and when D₂=“L”, S₃ is off and S₄ is on. During any set of switch settings, the control circuit senses the output voltage V_(out) of the power stage through resistor dividers R₁ and R₂, in comparison with a reference voltage V_(ref). Variations of V_(out) are sensed and amplified through the error amplifier (E/A). The output of the error amplifier E/A feeds the PWM comparator, and the output of the PWM comparator triggers the “L” state of D₁ or D₂ or both, according to the operation mode. Controlling power stage switches keep the output voltage V_(out) substantially in a predetermined relation with the reference voltage V_(ref).

The well-known current mode can also be employed in the embodiments of the present invention. In current mode control, the switch current or inductor current or other currents are measured and summed with the ramp signal. By feeding back the current info into the control loop, the line transient response and other dynamic characteristics are greatly improved.

The control circuit, as depicted in the embodiment of FIG. 1B, has three major blocks: (1) clock and ramp generator, (2) duty-cycle generator, and (3) mode detector. The clock and ramp generator generates two out-of-phase clock signals CLK₁ and CLK₂ and one RAMP signal. The phase delay of CLK₁ and CLK₂ is referred to as D_(b). The RAMP signal of this embodiment has a saw-tooth shape and is synchronized with CLK₁ or CLK₂.

The converter shown in FIG. 1 has three operation modes: (1) “BUCK” mode, (2) “BUCK-BOOST” mode, and (3) “BOOST” mode. The mode detector circuit checks D₁ at CLK₂ moment. If D₁=“L”, the circuit is in the “BUCK” mode; otherwise, it is in the “BUCK-BOOST” or the “BOOST” mode. The mode detector circuit also checks D₂ at CLK₁ moment. If D₂=“H”, the circuit is in the “BOOST” mode; otherwise, it is in “BUCK” or “BUCK-BOOST” mode.

After determining the operation mode of the converter, the mode detector circuit feeds mode signals BUCK and BST to duty-cycle generator circuit, and the BST signal to the clock and ramp generator circuit, wherein “BUCK” mode is when BUCK signal is “H” and BST signal is “L”; “BUCK-BOOST” mode is when BUCK signal is like inverting CLK2 and BST signal is “L” and “BOOST” mode is when BUCK signal is like inverting CLK2 and BST signal is “H”. According to the BST signal, the RAMP signal will smoothly extend when the circuit is entering into the “BOOST” mode, by adding a DC offset V_(os) to the RAMP signal.

The DC offset V_(os) is related to the phase delay of CLK₁ and CLK₂, and in this embodiment it is equal to D_(b)*V_(p), where V_(p) is the magnitude of the RAMP signal. The RAMP signal has a higher DC level in the “BOOST” mode than in the “BUCK” and the “BUCK-BOOST” mode. Among other signals discussed below, the RAMP signal is also fed to the PWM comparator. The duty-cycle generator circuit receives, as inputs, the mode signals BUCK and BST, clock signals CLK₁ and CLK₂, and the PWM comparator output ICMP.

The duty-cycle generator circuit identifies the operation mode according to the mode signals BUCK and BST. If the circuit is in the “BUCK” mode, CLK₁ triggers D₁ to “H”, and ICMP triggers D₁ to “L”; while D₂ stays “L”. If the circuit is in the “BOOST” mode, CLK₂ triggers D₂ to “H”, and ICMP triggers D₂ to “L”; while D1 stays “H”. If the circuit is in the “BUCK-BOOST” mode, CLK₁ triggers D₁ to “H”, CLK₂ triggers D₂ to “H”, and ICMP triggers both D₁ and D₂ to “L”.

FIG. 2 shows some of the operation waveforms of the automatic multimode converter shown in FIG. 1. When V_(in) is larger than V_(out), the circuit is in the “BUCK” mode. When V_(in) is close to the V_(out), the circuit is in the “BUCK-BOOST” mode. And when V_(in) is less than V_(out), the circuit is in the “BOOST” mode. The transitions of different modes are automatic and smooth.

FIG. 3 shows an example of implementation details of the automatic multimode converter shown in FIG. 1. FIG. 3 illustrates the details of embodiments of the duty-cycle generator, the clock and ramp generator, and the mode detector circuits.

FIG. 4 shows another example of implementation details of the automatic multimode converter shown in FIG. 1. This implementation example comprises the following two components:

First component, a power stage shown in FIG. 4A, including: one inductor, one input capacitor, one output capacitor, and four switches (S₁ through S₄), wherein S₁ and S₂ are actively controlled and wherein S₁ is referred to as the buck switch and S₂ as the boost switch. The other two switches can be either passively or actively controlled; and,

Second component, a control device shown in FIG. 4B, receiving feedback from the power stage and generating the control signals to drive at least two of the switches to modulate the output voltage and minimize power losses. The duty-cycle of the control signal for the buck switch is referred to as D₁, and the duty-cycle of the control signal for the boost switch is refereed as D₂. The control device checks D₁ and D₂ at CLK moments to determine the operation mode of the circuit so that the circuit can automatically operate between step-up and step-down conversions. The RAMP signal is automatically changed in different operation modes. In this embodiment the generation of D₁ and D₂ is also controlled by operation modes.

CONCLUSION

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” As used herein, the terms “connected,” “coupled,” or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling of connection between the elements can be physical, logical, or a combination thereof.

Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

Changes can be made to the invention in light of the above Detailed Description. While the above description describes certain embodiments of the invention, and describes the best mode contemplated, no matter how detailed the above appears in text, the invention can be practiced in many ways. Details of the compensation system described above may vary considerably in its implementation details, while still being encompassed by the invention disclosed herein.

As noted above, particular terminology used when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the invention with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention encompasses not only the disclosed embodiments, but also all equivalent ways of practicing or implementing the invention under the claims.

While certain aspects of the invention are presented below in certain claim forms, the inventors contemplate the various aspects of the invention in any number of claim forms. Accordingly, the inventors reserve the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the invention. 

1. A switch mode power supply (SMPS) operating from input voltages that are above, below, or equal to output voltages, the SMPS comprising: a power stage, including four switches S₁ 1, S₂, S₃, and S₄ for converting an input voltage V_(in) to an output voltage V_(out); a clock-and-ramp generator for generating at least two clock signals CLK₁ and CLK₂ and one ramp signal RAMP; a duty-cycle generator for generating at least two switching control signals D₁ and D₂ to control at least two of the four switches of the power stage so that to maintain the output voltage substantially in a predetermined relation with a reference voltage V_(ref), wherein the switching control signals are generated according to operation modes of the circuit; and a mode detector for detecting the operation modes of the circuit based on the clock and switching control signals.
 2. The SMPS of claim 1, wherein: S₁ is connected to an input voltage port; S₂ is connected to an output voltage port; an inductive element is connected between S₁ and S₂; S₃ is connected between a ground and a point of connection of S₁ and the inductive element; S₄ is connected between the ground and a point of connection of S₂ and the inductive element; a first switch driver controls S₁ and S₃ using D₁; and a second switch driver controls S₂ and S₄ using D₂.
 3. The SMPS of claim 2, wherein the switching control signals and corresponding switching actions comprise: when D₁ is High, S₁ is ON and S₃ is OFF; when D₁ is Low, S₁ is OFF and S₃ is ON; when D₂ is High, S₄ is ON and S₂ is OFF; and when D₂ is Low, S₄ is OFF and S₂ is ON.
 4. The SMPS of claim 1, wherein the operation mode is (1) “BUCK” mode when V_(in) is larger than V_(out), (2) “BOOST” mode when V_(in) is less than V_(out), or (3) “BUCK-BOOST” mode when V_(in) is close to the V_(out), and wherein if at CLK₂ moment D₁ is LOW, the circuit is in the “BUCK” mode; otherwise, it is in the “BUCK-BOOST” or the “BOOST” mode, and if at CLK₁ moment D₂ is HIGH, the circuit is in the “BOOST” mode; otherwise, it is in “BUCK” or “BUCK-BOOST” mode.
 5. The SMPS of claim 4, wherein the RAMP signal will smoothly extend according to the BST signal, by adding a DC offset V_(os)=D_(b)*V_(p) to the RAMP signal when the circuit is entering into the “BOOST” mode, wherein D_(b) is a phase between CLK₁ and CLK₂, and V_(p) is the RAMP signal magnitude, and wherein the RAMP signal has a higher DC level in the “BOOST” mode than in the “BUCK” and the “BUCK-BOOST” modes.
 6. The SMPS of claim 1, wherein the two clock signals generated by the clock-and-ramp generator are out-of-phase and the RAMP signal is a saw-tooth signal, and wherein the clock phase difference is used when a DC offset is computed and added to the RAMP signal.
 7. The SMPS of claim 1, wherein the duty-cycle generator generates two switching control signals and wherein each control signal controls two switches, and the control signals are generated based on: clock signals; indicator signals of the mode detector; and a function of the output voltage, wherein the function comprises: amplifying a difference between a scaled version of the output voltage and the reference voltage; and comparing the amplification result with the RAMP signal, or with a summation of the RAMP signal and a power stage current measurement, in a PWM (pulse-width modulation) comparator, wherein the comparison result is the desired function of the output voltage.
 8. The SMPS of claim 1, wherein only two of the power stage switches are actively controlled, and wherein an input capacitive element is connected between an input voltage port and the ground and an output capacitive element is connected between an output voltage port and the ground.
 9. A controlled switch mode power supply for operating from input voltages that are above, below, or equal to output voltages, the controlled switch mode power supply comprising: means for converting an input voltage V_(in) to an output voltage V_(out), further comprising four switches S₁, S₂, S₃, and S₄; means for generating two clock signals CLK₁ and CLK₂ and a ramp signal RAMP; means for generating two switching control signals D₁ and D₂ to control at least two of the four switches to maintain V_(out) at a predetermined value; and means for detecting operation modes and for generating two mode indicator signals “BUCK” and “BST”.
 10. The controlled switch mode power supply of claim 9, wherein only two of the switches of the voltage conversion means are actively controlled.
 11. The controlled switch mode power supply of claim 9, wherein: BST signal is utilized to generate CLK₁, CLK₂, and the RAMP signals; V_(out), BUCK, BST, CLK₁, CLK₂, and RAMP signals are utilized to generate D₁ and D₂ signals; D₁, D₂, CLK₁, and CLK₂ signals are utilized to generate BUCK and BST signals; and D₁ and D₂ signals are utilized to control at least two of the four switches S₁, S₂, S₃, and S₄.
 12. The controlled switch mode power supply of claim 11, wherein during a current mode control, in addition to the V_(out), BUCK, BST, CLK₁, CLK₂, and RAMP signals, a measurement of a current passing through S₁ is also utilized for the generation of D₁ and D₂ signals.
 13. A method of controlling a switch mode power supply to operate from input voltages that are above, below, or equal to output voltages, the method comprising: actively controlling at least two of four controllable switches S₁, S₂, S₃, and S₄ to convert an input voltage V_(in) to an output voltage V_(out); generating two clock signals CLK₁ and CLK₂ and one ramp signal RAMP; generating at least two switching control signals D₁ and D₂ to maintain the output voltage V_(out) substantially in a predetermined relation with a reference voltage V_(ref); and detecting operation modes and generating two mode indicator signals “BUCK” and “BST” that indicate relationships of the input and the output voltages.
 14. The method of claim 13, further comprising: utilizing the BST signal to generate clock and ramp signals; utilizing the BUCK and BST signals, along with the clock, the ramp, and the output voltage signals to generate the switching control signals D₁ and D₂; utilizing the switching control and the clock signals to generate the BUCK and BST indicator signals; and utilizing the switching control signals D₁ and D₂ to control the at least two of the four controllable switches S₁, S₂, S₃, and S₄.
 15. The method of claim 13, further comprising: connecting S₁ to an input voltage port; connecting S₂ to an output voltage port; connecting an inductive element between S₁ and S₂; connecting S₃ between a ground and a point of connection of S₁ and the inductive element; connecting S₄ between the ground and a point of connection of S₂ and the inductive element; controlling S₁ and S₃ by a first switch driver that receives the switching control signal D₁; and controlling S₂ and S₄ by a second switch driver that receives the switching control signal D₂.
 16. The method of claim 13, wherein the switching control signals perform the following corresponding switching actions: when D₁ is High, S₁ is ON and S₃ is OFF; when D₁ is Low, S₁ is OFF and S₃ is ON; when D₂ is High, S₄ is ON and S₂ is OFF; and when D₂ is Low, S₄ is OFF and S₂ is ON.
 17. The method of claim 14, wherein the operation mode is (1) “BUCK” mode when V_(in) is larger than V_(out), (2) “BOOST” mode when V_(in) is less than V_(out), or (3) “BUCK-BOOST” mode when V_(in) is close to the V_(out), and wherein if at CLK₂ moment D₁ is LOW, the circuit is in the “BUCK” mode; otherwise, it is in the “BUCK-BOOST” or the “BOOST” mode, and if at CLK₁ moment D₂ is HIGH, the circuit is in the “BOOST” mode; otherwise, it is in “BUCK” or “BUCK-BOOST” mode.
 18. The method of claim 17, wherein the RAMP signal is smoothly extended according to the BST signal, by adding a DC offset V_(os)=D_(b)*V_(p) to the RAMP signal when the circuit is entering into the “BOOST” mode, where D_(b) is a phase between CLK₁ and CLK₂, and V_(p) is the RAMP signal magnitude, and wherein the RAMP signal has a higher DC level in the “BOOST” mode than in the “BUCK” and the “BUCK-BOOST” modes.
 19. The method of claim 13, wherein the two clock signals are out-of-phase and the RAMP signal is a saw-tooth signal.
 20. The method of claim 13, wherein the switching control signals are generated based on: clock signals; BUCK and BST indicator signals; and a function of the output voltage, wherein the function comprises: amplifying a difference between a scaled version of the output voltage and the reference voltage; and comparing the amplification result with the RAMP signal, or with a summation of the RAMP signal with a power stage current measurement, in a PWM (pulse-width modulation) comparator, wherein the comparison result is the function of the output voltage.
 21. The method of claim 13, wherein an input capacitive element is connected between an input port and the ground and an output capacitive element is connected between an output port and the ground. 